Hi Baolin, Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on tip/timers/core] [also build test WARNING on v4.14 next-20171124] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Baolin-Wang/dt-bindings-clocksource-Add-Spreadtrum-SC9860-timer/20171125-090749 config: i386-allmodconfig (attached as .config) compiler: gcc-6 (Debian 6.4.0-9) 6.4.0 20171026 reproduce: # save the attached .config to linux build tree make ARCH=i386 All warnings (new ones prefixed by >>): In file included from arch/x86/include/asm/realmode.h:14:0, from arch/x86/include/asm/acpi.h:33, from arch/x86/include/asm/fixmap.h:19, from arch/x86/include/asm/apic.h:10, from arch/x86/include/asm/smp.h:12, from include/linux/smp.h:63, from include/linux/topology.h:33, from include/linux/gfp.h:8, from include/linux/idr.h:16, from include/linux/kernfs.h:14, from include/linux/sysfs.h:15, from include/linux/kobject.h:21, from include/linux/of.h:21, from include/linux/clocksource.h:18, from drivers/clocksource/sprd-timer.c:7: drivers/clocksource/sprd-timer.c: In function 'sprd_timer_update_counter': >> drivers/clocksource/sprd-timer.c:85:24: warning: right shift count >= width >> of type [-Wshift-count-overflow] writel_relaxed(cycles >> TIMER_VALUE_HI_SHIFT, ^ arch/x86/include/asm/io.h:87:39: note: in definition of macro 'writel_relaxed' #define writel_relaxed(v, a) __writel(v, a) ^ vim +85 drivers/clocksource/sprd-timer.c > 7 #include <linux/clocksource.h> 8 #include <linux/clockchips.h> 9 #include <linux/init.h> 10 #include <linux/interrupt.h> 11 #include <linux/sched_clock.h> 12 #include <linux/slab.h> 13 #include <linux/of.h> 14 #include <linux/of_address.h> 15 #include <linux/of_irq.h> 16 17 #define TIMER_NAME "sprd_timer" 18 19 #define TIMER_LOAD_LO 0x0 20 #define TIMER_LOAD_HI 0x4 21 #define TIMER_VALUE_LO 0x8 22 #define TIMER_VALUE_HI 0xc 23 24 #define TIMER_CTL 0x10 25 #define TIMER_CTL_PERIOD_MODE BIT(0) 26 #define TIMER_CTL_ENABLE BIT(1) 27 #define TIMER_CTL_64BIT_WIDTH BIT(16) 28 29 #define TIMER_INT 0x14 30 #define TIMER_INT_EN BIT(0) 31 #define TIMER_INT_RAW_STS BIT(1) 32 #define TIMER_INT_MASK_STS BIT(2) 33 #define TIMER_INT_CLR BIT(3) 34 35 #define TIMER_VALUE_SHDW_LO 0x18 36 #define TIMER_VALUE_SHDW_HI 0x1c 37 38 #define TIMER_VALUE_LO_MASK GENMASK(31, 0) 39 #define TIMER_VALUE_HI_SHIFT 32 40 41 struct sprd_timer_device { 42 struct clock_event_device ce; 43 void __iomem *base; 44 u32 freq; 45 int irq; 46 }; 47 48 static inline struct sprd_timer_device * 49 to_sprd_timer(struct clock_event_device *c) 50 { 51 return container_of(c, struct sprd_timer_device, ce); 52 } 53 54 static void sprd_timer_enable(struct sprd_timer_device *timer, u32 flag) 55 { 56 u32 val = readl_relaxed(timer->base + TIMER_CTL); 57 58 val |= TIMER_CTL_ENABLE; 59 if (flag & TIMER_CTL_64BIT_WIDTH) 60 val |= TIMER_CTL_64BIT_WIDTH; 61 else 62 val &= ~TIMER_CTL_64BIT_WIDTH; 63 64 if (flag & TIMER_CTL_PERIOD_MODE) 65 val |= TIMER_CTL_PERIOD_MODE; 66 else 67 val &= ~TIMER_CTL_PERIOD_MODE; 68 69 writel_relaxed(val, timer->base + TIMER_CTL); 70 } 71 72 static void sprd_timer_disable(struct sprd_timer_device *timer) 73 { 74 u32 val = readl_relaxed(timer->base + TIMER_CTL); 75 76 val &= ~TIMER_CTL_ENABLE; 77 writel_relaxed(val, timer->base + TIMER_CTL); 78 } 79 80 static void sprd_timer_update_counter(struct sprd_timer_device *timer, 81 unsigned long cycles) 82 { 83 writel_relaxed(cycles & TIMER_VALUE_LO_MASK, 84 timer->base + TIMER_LOAD_LO); > 85 writel_relaxed(cycles >> TIMER_VALUE_HI_SHIFT, 86 timer->base + TIMER_LOAD_HI); 87 } 88 --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation
.config.gz
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