tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
head: 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323
commit: eb813999f20097d24310836dfa07a97e2eb0c936 drm/nouveau/mmu: implement new
vmm backend
date: 4 weeks ago
coccinelle warnings: (new ones prefixed by >>)
>> drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c:550:2-3: Unneeded semicolon
vim +550 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c
466
467 static inline u64
468 nvkm_vmm_iter(struct nvkm_vmm *vmm, const struct nvkm_vmm_page *page,
469 u64 addr, u64 size, const char *name, bool ref,
470 bool (*REF_PTES)(struct nvkm_vmm_iter *, u32, u32),
471 nvkm_vmm_pte_func MAP_PTES, struct nvkm_vmm_map *map,
472 nvkm_vmm_pxe_func CLR_PTES)
473 {
474 const struct nvkm_vmm_desc *desc = page->desc;
475 struct nvkm_vmm_iter it;
476 u64 bits = addr >> page->shift;
477
478 it.page = page;
479 it.desc = desc;
480 it.vmm = vmm;
481 it.cnt = size >> page->shift;
482 it.flush = NVKM_VMM_LEVELS_MAX;
483
484 /* Deconstruct address into PTE indices for each mapping level.
*/
485 for (it.lvl = 0; desc[it.lvl].bits; it.lvl++) {
486 it.pte[it.lvl] = bits & ((1 << desc[it.lvl].bits) - 1);
487 bits >>= desc[it.lvl].bits;
488 }
489 it.max = --it.lvl;
490 it.pt[it.max] = vmm->pd;
491
492 it.lvl = 0;
493 TRA(&it, "%s: %016llx %016llx %d %lld PTEs", name,
494 addr, size, page->shift, it.cnt);
495 it.lvl = it.max;
496
497 /* Depth-first traversal of page tables. */
498 while (it.cnt) {
499 struct nvkm_vmm_pt *pgt = it.pt[it.lvl];
500 const int type = desc->type == SPT;
501 const u32 pten = 1 << desc->bits;
502 const u32 ptei = it.pte[0];
503 const u32 ptes = min_t(u64, it.cnt, pten - ptei);
504
505 /* Walk down the tree, finding page tables for each
level. */
506 for (; it.lvl; it.lvl--) {
507 const u32 pdei = it.pte[it.lvl];
508 struct nvkm_vmm_pt *pgd = pgt;
509
510 /* Software PT. */
511 if (ref &&
NVKM_VMM_PDE_INVALID(pgd->pde[pdei])) {
512 if (!nvkm_vmm_ref_swpt(&it, pgd, pdei))
513 goto fail;
514 }
515 it.pt[it.lvl - 1] = pgt = pgd->pde[pdei];
516
517 /* Hardware PT.
518 *
519 * This is a separate step from above due to
GF100 and
520 * newer having dual page tables at some
levels, which
521 * are refcounted independently.
522 */
523 if (ref && !pgt->refs[desc[it.lvl - 1].type ==
SPT]) {
524 if (!nvkm_vmm_ref_hwpt(&it, pgd, pdei))
525 goto fail;
526 }
527 }
528
529 /* Handle PTE updates. */
530 if (!REF_PTES || REF_PTES(&it, ptei, ptes)) {
531 struct nvkm_mmu_pt *pt = pgt->pt[type];
532 if (MAP_PTES || CLR_PTES) {
533 if (MAP_PTES)
534 MAP_PTES(vmm, pt, ptei, ptes,
map);
535 else
536 CLR_PTES(vmm, pt, ptei, ptes);
537 nvkm_vmm_flush_mark(&it);
538 }
539 }
540
541 /* Walk back up the tree to the next position. */
542 it.pte[it.lvl] += ptes;
543 it.cnt -= ptes;
544 if (it.cnt) {
545 while (it.pte[it.lvl] == (1 <<
desc[it.lvl].bits)) {
546 it.pte[it.lvl++] = 0;
547 it.pte[it.lvl]++;
548 }
549 }
> 550 };
551
552 nvkm_vmm_flush(&it);
553 return ~0ULL;
554
555 fail:
556 /* Reconstruct the failure address so the caller is able to
557 * reverse any partially completed operations.
558 */
559 addr = it.pte[it.max--];
560 do {
561 addr = addr << desc[it.max].bits;
562 addr |= it.pte[it.max];
563 } while (it.max--);
564
565 return addr << page->shift;
566 }
567
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