[PATCH AUTOSEL for 4.9 116/156] clk: tegra: Fix cclk_lp divisor register

[alexander . levin]

From: Michał Mirosław <mirq-li...@rere.qmqm.pl>

[ Upstream commit 54eff2264d3e9fd7e3987de1d7eba1d3581c631e ]

According to comments in code and common sense, cclk_lp uses its
own divisor, not cclk_g's.

Fixes: b08e8c0ecc42 ("clk: tegra: add clock support for Tegra30")
Signed-off-by: Michał Mirosław <mirq-li...@rere.qmqm.pl>
Acked-By: Peter De Schrijver <pdeschrij...@nvidia.com>
Signed-off-by: Thierry Reding <tred...@nvidia.com>
Signed-off-by: Sasha Levin <alexander.le...@verizon.com>
---
 drivers/clk/tegra/clk-tegra30.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 8e2db5ead8da..af520d81525f 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -963,7 +963,7 @@ static void __init tegra30_super_clk_init(void)
         * U71 divider of cclk_lp.
         */
        clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3",
-                               clk_base + SUPER_CCLKG_DIVIDER, 0,
+                               clk_base + SUPER_CCLKLP_DIVIDER, 0,
                                TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
        clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL);
 
-- 
2.11.0