On 11/12/17 09:30, Rasmus Villemoes wrote: > On 2017-12-08 17:02, Marc Zyngier wrote:
[...] >> Overall, it is a bit annoying that you just copied the driver altogether >> instead of trying to allow the common stuff to be shared between >> drivers. Most of this is just boilerplate code... > > Yes, it did annoy me as well. However, the real meat of this is which > bits of which register to poke to support a negative polarity irq, and > there doesn't seem to be a good way to express that in DT. The register > offset and the mapping from external irq# to the GIC one is reasonably > easy (and would thus get rid of my NIRQ and INTPCR macros), but > describing the mapping from IRQ# to the bit that needs to be set (or > cleared) seems much harder. I cannot generalize from one example, so > lacking documentation for any other Layerscape SOC, whatever I might > come up with might not actually be useful for other hardware, making it > rather pointless. But if you have any suggestions for how the DT > bindings might look, I'm all ears. You could have a list of <bit irq> pairs defining the mapping, for example. But I'd encourage you to get in touch with the Freescale/NXP folks and find out how this HW works. get_maintainers.pl gives me this: Shawn Guo <[email protected]> Tang Yuantian <[email protected]> Hou Zhiqiang <[email protected]> Madalin Bucur <[email protected]> Minghuan Lian <[email protected]> Yuantian Tang <[email protected]> Yangbo Lu <[email protected]> "Horia Geantă" <[email protected]> I suggest you spam them and find out. Thanks, M. -- Jazz is not dead. It just smells funny...
