On Tue, 2017-12-19 at 16:23 +0100, Peter Zijlstra wrote: > On Tue, Dec 19, 2017 at 06:48:24PM +0800, Zhang Rui wrote: > > > > On Mon, 2017-12-18 at 21:28 +0100, Peter Zijlstra wrote: > > > > > > Hi, can you see if this makes you Surface boot? > > > > > No, it does not boot. > So I'm confused on the lapic calibration. > > That stuff uses global_clock_event, which is initially the i8253 > (PIT), > but because !PIC this thing won't be there either on your platform. > > Then we initialize I/O APIC, and your machine has: > > [ 0.000000] IOAPIC[0]: apic_id 2, version 32, address 0xfec00000, > GSI 0-119 > [ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl > dfl) > [ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high > level) > [ 0.000000] ACPI: IRQ0 used by override. > [ 0.000000] ACPI: IRQ9 used by override. > > So your ACPI table has an override for IRQ2 and routes it to IRQ0. > > Then we initialize HPET, and we _always_ do hpet_enable_legacy_int(), > which sets the LegacyRouting bit.
Right. > The HPET document says: > > If the ENABLE_CNF bit and the LEG_RT_CNF bit are both set, then the > interrupts will be routed as follows: > > Timer 0 will be routed to IRQ0 in Non-APIC or IRQ2 in the I/O > APIC But AFAICS, the HPET emulated timer interrupts goes to IRQ0 on all the machines I have tested, but on this MS Surface Pro 4, there is no irq 0 row in /proc/interrupts. $ cat /proc/interrupts CPU0 CPU1 CPU2 CPU3 8: 0 1 0 0 IR-IO-APIC 8- edge rtc0 9: 476 144 4573 132 IR-IO-APIC 9- fasteoi acpi 14: 0 0 0 0 IR-IO-APIC 14- edge INT344B:00 16: 646 4971 63574 3973 IR-IO-APIC 16- fasteoi idma64.0, MRVL_PCIE, i2c_designware.0 17: 0 0 0 0 IR-IO-APIC 17- fasteoi idma64.1, i2c_designware.1 18: 0 0 0 0 IR-IO-APIC 18- fasteoi idma64.2, i2c_designware.2 19: 0 0 0 0 IR-IO-APIC 19- fasteoi idma64.3, i2c_designware.3 Maybe I need to check if IRQ0 is overridden on other platforms, if no, registering to IRQ2 for HPET Timer 0 could help in this case? > Timer 1 will be routed to IRQ8 in Non-APIC or IRQ8 in the I/O > APIC > Timer 2-n will be routed as per the routing in the timer n config > registers. > > If the LegacyReplacement Route bit is set, the individual routing > bits > for timers 0 and 1 (APIC or FSB) will have no impact. > > And then we set global_clock_event to &hpet_clockevent. Yes, I can confirm this. > > At this point that _SHOULD_ work afaict, even without actual PIC > present. so IOAPIC is ready when we calibrating Lapic timer? > > Sometime after that we call into calibrate_APIC_clock() -- because > !TSC_DEADLINE -- and this is where you get stuck, because > global_clock_event is not in fact delivering interrupts. right. > > Thomas may have more clue, we'll have to wait for him to have a > time-slot available. okay. thanks, rui
