From: Fenghua Yu <fenghua...@intel.com> L2 CDP enables isolation and prioritization of code and data individually within the L2 cache. The feature is enumerated in CPUID.(EAX=0x10, ECX=2):ECX.CDP[bit 2] and enabled in bit 0 of MSR IA32_L2_QOS_CFG at address 0xc82.
As with L3 CDP, when L2 CDP is enabled, each CLOS is mapped 1:2 with mask MSRs, with one mask enabling programmatic control over data fill location and one mask control over data placement. The feature is enabled in kernel along with other RDT features. More detailed L2 CDP hardware information can be found in technical article: https://software.intel.com/en-us/articles/intel-resource-director-technology-extensions-introducing-the-l2-code-and-data The first patch fixes a documentation issue. The following five patches do the real work. The patches are based on x86/cache branch in tip tree. The patch #3 cannot be applied to upstream now because of reformatting in arch/x86/include/asm /cpufeatures.h. But it's easy to rebase the patches to upstream. Fenghua Yu (6): x86/intel_rdt: Classify /proc/cpuinfo flag bits and add missing bits in documentation x86/intel_rdt: Add L2 Code and Data Prioritization (CDP) support in documentation x86/intel_rdt: Enumerate L2 Code and Data Prioritization (CDP) feature x86/intel_rdt: Add two new resources for L2 Code and Data Prioritization (CDP) x86/intel_rdt: Enable L2 CDP in MSR IA32_L2_QOS_CFG x86/intel_rdt: Turn on/off L2 CDP in kernel parameter Documentation/admin-guide/kernel-parameters.txt | 3 +- Documentation/x86/intel_rdt_ui.txt | 14 ++- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/intel_rdt.c | 68 ++++++++++++-- arch/x86/kernel/cpu/intel_rdt.h | 5 + arch/x86/kernel/cpu/intel_rdt_rdtgroup.c | 117 ++++++++++++++++++------ arch/x86/kernel/cpu/scattered.c | 1 + 7 files changed, 170 insertions(+), 39 deletions(-) -- 1.8.3.1
