This patch set introduces a PCI-X / PCI-Express read byte count control 
interface. Instead of letting every driver to directly read/write to PCI 
config space for that, an interface is provided. The interface functions then 
can be used for quirks since some PCI bridges require that read byte count 
values are set by the BIOS and left unchanged by device drivers.

Patch 1/2: PCI subsystem
Patch 2/2: affected drivers

Both patches are based on work by Stephen Hemminger, please see
http://lkml.org/lkml/2006/12/8/222

Regards,
Peter Oruba

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General Partner authorized to represent:
AMD Saxony LLC (Wilmington, Delaware, US)
General Manager of AMD Saxony LLC: Dr. Hans-R. Deppe, Thomas McCoy


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