On Wed, Jan 03, 2018 at 11:16:48AM +0200, Meelis Roos wrote:
> ---[ ESPfix Area ]---
> 0xffffff0000000000-0xffffff1800000000 96G
> pud
> 0xffffff1800000000-0xffffff1800009000 36K
> pte
> 0xffffff1800009000-0xffffff180000a000 4K ro
> NX pte
> 0xffffff180000a000-0xffffff1800019000 60K
> pte
> 0xffffff1800019000-0xffffff180001a000 4K ro
> NX pte
> 0xffffff180001a000-0xffffff1800029000 60K
> pte
> 0xffffff1800029000-0xffffff180002a000 4K ro
> NX pte
> 0xffffff180002a000-0xffffff1800039000 60K
> pte
> 0xffffff1800039000-0xffffff180003a000 4K ro
> NX pte
> 0xffffff180003a000-0xffffff1800049000 60K
> pte
> 0xffffff1800049000-0xffffff180004a000 4K ro
> NX pte
> 0xffffff180004a000-0xffffff1800059000 60K
> pte
> 0xffffff1800059000-0xffffff180005a000 4K ro
> NX pte
> 0xffffff180005a000-0xffffff1800069000 60K
> pte
> 0xffffff1800069000-0xffffff180006a000 4K ro
> NX pte
> 0xffffff180006a000-0xffffff1800079000 60K
> pte
> ... 131059 entries skipped ...
> ---[ High Kernel Mapping ]---
> 0xffffffff80000000-0xffffffff81e00000 30M
> pmd
> 0xffffffff81e00000-0xffffffff82000000 2M ro PSE GLB
> x pmd
Ha, this must be it. What I said yesterday about the guard hole
hypervisor range was wrong because we're looking at VA slice [47:12] and
this one matches:
Hex: 0xffffffff81e00000
1111_1111_1111_1111_1111_1111_1111_1111_1000_0001_1110_0000_0000_0000_0000_0000
63 59 55 51 47 43 39 35 31 27 23 19 15 11 7 3
Hex: 0x0000ffff81e000e0
0000_0000_0000_0000_1111_1111_1111_1111_1000_0001_1110_0000_0000_0000_1110_0000
63 59 55 51 47 43 39 35 31 27 23 19 15 11 7 3
So that's at offset 0xe0 in that 2M page in the high kernel mapping.
tglx, ideas?
--
Regards/Gruss,
Boris.
Good mailing practices for 400: avoid top-posting and trim the reply.
