Commit-ID: 0592b0bce1694957fed178fc52f4b11576714b07 Gitweb: https://git.kernel.org/tip/0592b0bce1694957fed178fc52f4b11576714b07 Author: Tom Lendacky <thomas.lenda...@amd.com> AuthorDate: Fri, 5 Jan 2018 10:07:46 -0600 Committer: Thomas Gleixner <t...@linutronix.de> CommitDate: Sat, 6 Jan 2018 21:57:40 +0100
x86/cpu/AMD: Make LFENCE a serializing instruction To aid in speculation control, make LFENCE a serializing instruction. This is done by setting bit 1 of MSR 0xc0011029 (DE_CFG). Some families that support LFENCE do not have this MSR. For these families, the LFENCE instruction is already serializing. Signed-off-by: Tom Lendacky <thomas.lenda...@amd.com> Signed-off-by: Thomas Gleixner <t...@linutronix.de> Reviewed-by: Borislav Petkov <b...@alien8.de> Cc: Peter Zijlstra <pet...@infradead.org> Cc: Linus Torvalds <torva...@linux-foundation.org> Cc: Dave Hansen <dave.han...@intel.com> Cc: Tim Chen <tim.c.c...@linux.intel.com> Cc: Greg Kroah-Hartman <gre...@linux-foundation.org> Cc: David Woodhouse <d...@amazon.co.uk> Cc: Paul Turner <p...@google.com> Cc: sta...@vger.kernel.org Link: https://lkml.kernel.org/r/20180105160746.23786.11850.st...@tlendack-t1.amdoffice.net --- arch/x86/include/asm/msr-index.h | 2 ++ arch/x86/kernel/cpu/amd.c | 9 +++++++++ 2 files changed, 11 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index ab02261..1e7d710 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -352,6 +352,8 @@ #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL #define FAM10H_MMIO_CONF_BASE_SHIFT 20 #define MSR_FAM10H_NODE_ID 0xc001100c +#define MSR_F10H_DECFG 0xc0011029 +#define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT 1 /* K8 MSRs */ #define MSR_K8_TOP_MEM1 0xc001001a diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index bcb75dc..fbd439e 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -829,6 +829,15 @@ static void init_amd(struct cpuinfo_x86 *c) set_cpu_cap(c, X86_FEATURE_K8); if (cpu_has(c, X86_FEATURE_XMM2)) { + /* + * Use LFENCE for execution serialization. On families which + * don't have that MSR, LFENCE is already serializing. + * msr_set_bit() uses the safe accessors, too, even if the MSR + * is not present. + */ + msr_set_bit(MSR_F10H_DECFG, + MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT); + /* MFENCE stops RDTSC speculation */ set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); }
