On Fri, Jan 12, 2018 at 1:15 PM, <[email protected]> wrote: > From: Patrice Chotard <[email protected]> > > Two mask registers are used in order to select which events have to > actually generate an interrupt on each IRQ line. > > It seems that in the single-IRQ case it's assumed that the IRQs lines > are simply OR-ed, while the two mask registers are still present. The > driver still programs the two mask registers separately. > > However the STM32 variant has only one IRQ, and also has only one mask > register. > > This patch prepares for STM32 variant support by making the driver using > only one mask register. > > This patch also optimize the MMCIMASK1 mask usage by caching it into > host->mask1_reg which avoid to read it into mmci_irq(). > > Tested only on STM32 variant. RFT for variants other than STM32 > > Signed-off-by: Andrea Merello <[email protected]> > Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Linus Walleij <[email protected]> Yours, Linus Walleij
