Hi Jacopo, Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on linus/master] [also build test WARNING on v4.15-rc8] [cannot apply to linuxtv-media/master next-20180119] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Jacopo-Mondi/Renesas-Capture-Engine-Unit-CEU-V4L2-driver/20180120-053007 config: ia64-allmodconfig (attached as .config) compiler: ia64-linux-gcc (GCC) 7.2.0 reproduce: wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # save the attached .config to linux build tree make.cross ARCH=ia64 Note: it may well be a FALSE warning. FWIW you are at least aware of it now. http://gcc.gnu.org/wiki/Better_Uninitialized_Warnings All warnings (new ones prefixed by >>): drivers/media/platform/renesas-ceu.c: In function 'ceu_start_streaming': >> drivers/media/platform/renesas-ceu.c:287:2: warning: 'cdwdr' may be used >> uninitialized in this function [-Wmaybe-uninitialized] iowrite32(data, priv->base + reg_offs); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/media/platform/renesas-ceu.c:335:27: note: 'cdwdr' was declared here u32 camcr, cdocr, cfzsr, cdwdr, capwr; ^~~~~ >> drivers/media/platform/renesas-ceu.c:287:2: warning: 'cfzsr' may be used >> uninitialized in this function [-Wmaybe-uninitialized] iowrite32(data, priv->base + reg_offs); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/media/platform/renesas-ceu.c:335:20: note: 'cfzsr' was declared here u32 camcr, cdocr, cfzsr, cdwdr, capwr; ^~~~~ >> drivers/media/platform/renesas-ceu.c:415:8: warning: 'camcr' may be used >> uninitialized in this function [-Wmaybe-uninitialized] camcr |= mbus_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW ? 1 << 0 : 0; ~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/media/platform/renesas-ceu.c:335:6: note: 'camcr' was declared here u32 camcr, cdocr, cfzsr, cdwdr, capwr; ^~~~~ drivers/media/platform/renesas-ceu.c: In function 'ceu_probe': >> drivers/media/platform/renesas-ceu.c:1621:9: warning: 'ret' may be used >> uninitialized in this function [-Wmaybe-uninitialized] return ret; ^~~ vim +/cdwdr +287 drivers/media/platform/renesas-ceu.c 284 285 static void ceu_write(struct ceu_device *priv, unsigned int reg_offs, u32 data) 286 { > 287 iowrite32(data, priv->base + reg_offs); 288 } 289 290 static u32 ceu_read(struct ceu_device *priv, unsigned int reg_offs) 291 { 292 return ioread32(priv->base + reg_offs); 293 } 294 295 /* 296 * ceu_soft_reset() - Software reset the CEU interface. 297 * @ceu_device: CEU device. 298 * 299 * Returns 0 for success, -EIO for error. 300 */ 301 static int ceu_soft_reset(struct ceu_device *ceudev) 302 { 303 unsigned int i; 304 305 ceu_write(ceudev, CEU_CAPSR, CEU_CAPSR_CPKIL); 306 307 for (i = 0; i < 100; i++) { 308 if (!(ceu_read(ceudev, CEU_CSTSR) & CEU_CSTRST_CPTON)) 309 break; 310 udelay(1); 311 } 312 313 if (i == 100) { 314 dev_err(ceudev->dev, "soft reset time out\n"); 315 return -EIO; 316 } 317 318 for (i = 0; i < 100; i++) { 319 if (!(ceu_read(ceudev, CEU_CAPSR) & CEU_CAPSR_CPKIL)) 320 return 0; 321 udelay(1); 322 } 323 324 /* If we get here, CEU has not reset properly. */ 325 return -EIO; 326 } 327 328 /* --- CEU Capture Operations --- */ 329 330 /* 331 * ceu_hw_config() - Configure CEU interface registers. 332 */ 333 static int ceu_hw_config(struct ceu_device *ceudev) 334 { > 335 u32 camcr, cdocr, cfzsr, cdwdr, capwr; 336 struct v4l2_pix_format_mplane *pix = &ceudev->v4l2_pix; 337 struct ceu_subdev *ceu_sd = ceudev->sd; 338 struct ceu_mbus_fmt *mbus_fmt = &ceu_sd->mbus_fmt; 339 unsigned int mbus_flags = ceu_sd->mbus_flags; 340 341 /* Start configuring CEU registers */ 342 ceu_write(ceudev, CEU_CAIFR, 0); 343 ceu_write(ceudev, CEU_CFWCR, 0); 344 ceu_write(ceudev, CEU_CRCNTR, 0); 345 ceu_write(ceudev, CEU_CRCMPR, 0); 346 347 /* Set the frame capture period for both image capture and data sync. */ 348 capwr = (pix->height << 16) | pix->width * mbus_fmt->bpp / 8; 349 350 /* 351 * Swap input data endianness by default. 352 * In data fetch mode bytes are received in chunks of 8 bytes. 353 * D0, D1, D2, D3, D4, D5, D6, D7 (D0 received first) 354 * The data is however by default written to memory in reverse order: 355 * D7, D6, D5, D4, D3, D2, D1, D0 (D7 written to lowest byte) 356 * 357 * Use CEU_CDOCR[2:0] to swap data ordering. 358 */ 359 cdocr = CEU_CDOCR_SWAP_ENDIANNESS; 360 361 /* 362 * Configure CAMCR and CDOCR: 363 * match input components ordering with memory output format and 364 * handle downsampling to YUV420. 365 * 366 * If the memory output planar format is 'swapped' (Cr before Cb) and 367 * input format is not, use the swapped version of CAMCR.DTARY. 368 * 369 * If the memory output planar format is not 'swapped' (Cb before Cr) 370 * and input format is, use the swapped version of CAMCR.DTARY. 371 * 372 * CEU by default downsample to planar YUV420 (CDCOR[4] = 0). 373 * If output is planar YUV422 set CDOCR[4] = 1 374 * 375 * No downsample for data fetch sync mode. 376 */ 377 switch (pix->pixelformat) { 378 /* Data fetch sync mode */ 379 case V4L2_PIX_FMT_YUYV: 380 /* TODO: handle YUYV permutations through DTARY bits. */ 381 camcr = CEU_CAMCR_JPEG; 382 cdocr |= CEU_CDOCR_NO_DOWSAMPLE; 383 cfzsr = (pix->height << 16) | pix->width; 384 cdwdr = pix->plane_fmt[0].bytesperline; 385 break; 386 387 /* Non-swapped planar image capture mode. */ 388 case V4L2_PIX_FMT_NV16: 389 cdocr |= CEU_CDOCR_NO_DOWSAMPLE; 390 case V4L2_PIX_FMT_NV12: 391 if (mbus_fmt->swapped) 392 camcr = mbus_fmt->fmt_order_swap; 393 else 394 camcr = mbus_fmt->fmt_order; 395 396 cfzsr = (pix->height << 16) | pix->width; 397 cdwdr = pix->width; 398 break; 399 400 /* Swapped planar image capture mode. */ 401 case V4L2_PIX_FMT_NV61: 402 cdocr |= CEU_CDOCR_NO_DOWSAMPLE; 403 case V4L2_PIX_FMT_NV21: 404 if (mbus_fmt->swapped) 405 camcr = mbus_fmt->fmt_order; 406 else 407 camcr = mbus_fmt->fmt_order_swap; 408 409 cfzsr = (pix->height << 16) | pix->width; 410 cdwdr = pix->width; 411 break; 412 } 413 414 camcr |= mbus_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW ? 1 << 1 : 0; > 415 camcr |= mbus_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW ? 1 << 0 : 0; 416 417 /* TODO: handle 16 bit bus width with DTIF bit in CAMCR */ 418 ceu_write(ceudev, CEU_CAMCR, camcr); 419 ceu_write(ceudev, CEU_CDOCR, cdocr); 420 ceu_write(ceudev, CEU_CAPCR, CEU_CAPCR_BUS_WIDTH256); 421 422 /* 423 * TODO: make CAMOR offsets configurable. 424 * CAMOR wants to know the number of blanks between a VS/HS signal 425 * and valid data. This value should actually come from the sensor... 426 */ 427 ceu_write(ceudev, CEU_CAMOR, 0); 428 429 /* TODO: 16 bit bus width require re-calculation of cdwdr and cfzsr */ 430 ceu_write(ceudev, CEU_CAPWR, capwr); 431 ceu_write(ceudev, CEU_CFSZR, cfzsr); 432 ceu_write(ceudev, CEU_CDWDR, cdwdr); 433 434 return 0; 435 } 436 --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation
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