From: Florian Fainelli <florian.faine...@broadcom.com>
Some boards may have to override how the TLB initialization is done,
e.g: to support eXtended Kseg0/1 features on Broadcom BMIPS boards.
Allow this to happen by providing a board_tlb_init() hook.
Signed-off-by: Florian Fainelli <f.faine...@gmail.com>
---
arch/mips/include/asm/traps.h | 1 +
arch/mips/kernel/traps.c | 6 +++++-
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/traps.h b/arch/mips/include/asm/traps.h
index f41cf3ee82a7..66c9c855be6e 100644
--- a/arch/mips/include/asm/traps.h
+++ b/arch/mips/include/asm/traps.h
@@ -26,6 +26,7 @@ extern void (*board_ejtag_handler_setup)(void);
extern void (*board_bind_eic_interrupt)(int irq, int regset);
extern void (*board_ebase_setup)(void);
extern void (*board_cache_error_setup)(void);
+extern void (*board_tlb_init)(void);
extern int register_nmi_notifier(struct notifier_block *nb);
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 5d19ed07e99d..b03864eb8213 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -106,6 +106,7 @@ void (*board_ejtag_handler_setup)(void);
void (*board_bind_eic_interrupt)(int irq, int regset);
void (*board_ebase_setup)(void);
void(*board_cache_error_setup)(void);
+void (*board_tlb_init)(void);
static void show_raw_backtrace(unsigned long reg29)
{
@@ -2230,7 +2231,10 @@ void per_cpu_trap_init(bool is_boot_cpu)
/* Boot CPU's cache setup in setup_arch(). */
if (!is_boot_cpu)
cpu_cache_init();
- tlb_init();
+ if (board_tlb_init)
+ board_tlb_init();
+ else
+ tlb_init();
TLBMISS_HANDLER_SETUP();
}
--
2.7.4
