On Fri, Jan 26, 2018 at 10:41:58AM +0800, Jason Wang wrote: > > > On 2018年01月26日 01:11, Michael S. Tsirkin wrote: > > On Thu, Jan 25, 2018 at 09:49:22AM -0500, Paolo Bonzini wrote: > > > > > Michael and Jason, any progress on implementing a fast virtio > > > > > mechanism > > > > > that doesn't rely on undefined behavior? > > > > > > > > > > (Encode writing instruction length into last 4 bits of MMIO address, > > > > > side-channel say that accesses to the MMIO area always use certain > > > > > instruction length, use hypercall, ...) > > > > > > > > > > Thanks. > > > > No progress from my side. But we can use PIO for virtio 1.0 and it's > > > > faster than fast MMIO (qemu supports modern pio notification bar, we can > > > > make it as default). It looks to me that neither encoding nor hypercall > > > > will work for real hardware virtio device. > > > Encoding the instruction length would work, the h/w virtio devices would > > > just ignore it. But... it is really ugly. > > > > > > Using PIO would be a small step backwards for PCIe. As long as the device > > > only needs *one* notification register (either MMIO or PIO) to initialize > > > successfully, it's okay. Then if there is no PIO space you'd just fall > > > back > > > to the slower MMIO notification. > > > > > > Paolo > > A bigger issue for PIO is it's causing exits for hw devices. > > > > > > Just to make sure I understand. For exits you mean vmexit? I believe MMIO > will cause vmexit too. > > Thanks
Not with an assigned device where the PTE is marked as present, it won't. -- MST
