On 02/12/2018 04:10 PM, Timur Tabi wrote: > On 02/12/2018 05:57 PM, Florian Fainelli wrote: >> That is debatable, is there a good publicly available table of what the >> typical L1 cache line size is on ARMv8 platforms? > > I don't have that, but I was under the impression that we moved from 6 > to 7 because more and more ARMv8 platforms have 128-byte caches, so that > is the "new normal". >
That does not seem to be the data that I am collecting from ARM's website and some quick googling: The following cores appear to have a 64bytes L1D cache line size: A55, A73 (fixed), A35, A32, A53, A57 (fixed), A72 (fixed) even the Falkor seems to be that way according to [1]. APM Mustang also seems to be 64b L1D according to [2]. [1]: https://en.wikichip.org/wiki/qualcomm/microarchitectures/falkor [2]: http://www.7-cpu.com/cpu/X-Gene.html And then we seem to covering what the ARM64 mainline kernel knows about non-ARM implementations: ThunderX and ThunderX2 (formerly Broadcom Vulcan). There is possibly the Qualcomm Kryo is different, but wikipedia seems to suggest it is a derivative of existing Cortex-A CPUs which have a 64b cache line size. Let's see what Catalin and Will think about what the default should be. Thanks! -- Florian
