On Wed, May 23, 2007 at 11:26:53AM -0700, Yu, Fenghua wrote: > > elements are cacheline aligned. And as such, this differentiates the > local > > only data and remotely accessed data cleanly. > > >OK, but could we please have a concise description of the impact > >of these changes on kernel memory footprint? Increase or decrease? > >And by approximately how much? > > Depending on how linker places percpu data, the patches could > increase or decrease percpu section size. Data from 2.6.21-rc7-mm2: > > On x86 SMP, the section size is increased from 0x7768 to 0x790c. > 1.3% increase. > > On X86-64 SMP, the size is decreased from 0x72d0 to 0x6540. > 11.8% decrease. > > On X86-64 VSMP, the size is increased from 0x72d0 to 0x8340. > 14.3% increase. > > On IA64 SMP, the size is decreased from 0x8370 to 0x7fc0. > 2.8% decrease.
Has there been any measurable benefit yet due to tail padding? It would also be interesting to check the wastage/savings on another large cache architecture like S390 (which has a 256 byte cache line) Thanks, Kiran - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/