Microcode updates can be safer if the caches are clean. Some of the issues around in certain Broadwell parts can be addressed by doing a full cache flush.
Signed-off-by: Ashok Raj <[email protected]> Cc: X86 ML <[email protected]> Cc: LKML <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: Ingo Molnar <[email protected]> Cc: Tony Luck <[email protected]> Cc: Andi Kleen <[email protected]> Cc: Boris Petkov <[email protected]> Cc: Tom Lendacky <[email protected]> Cc: Arjan Van De Ven <[email protected]> --- arch/x86/kernel/cpu/microcode/intel.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index 137c9f5..50e48c4 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -601,6 +601,13 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) return UCODE_OK; } + /* + * Microcode updates can be safer if the caches are clean. + * Some of the issues around in certain Broadwell parts + * can be addressed by doing a full cache flush. + */ + native_wbinvd(); + /* write microcode via MSR 0x79 */ native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); @@ -817,6 +824,13 @@ static enum ucode_state apply_microcode_intel(int cpu) return UCODE_OK; } + /* + * Microcode updates can be safer if the caches are clean. + * Some of the issues around in certain Broadwell parts + * can be addressed by doing a full cache flush. + */ + wbinvd(); + /* write microcode via MSR 0x79 */ wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); -- 2.7.4
