Andi Kleen <[EMAIL PROTECTED]> writes: > On Friday 25 May 2007 06:26:50 Eric W. Biederman wrote: >> >> This patch is the result of a quick survey of the Intel chipset >> documents. I took a quick look in the document to see if the chipset >> supported MSI and if so I looked through to find the vendor and device >> id of device 0 function 0 of the chipset and added a quirk for that >> device id if I it was not a duplicate. > > It would be better to look for any PCI bridge. Sometimes there are > different PCI bridges around (e.g. external PCI-X bridges on HT systems) > which might need own quirks
Maybe but pci-pci bridges should have no problems with MSI traffic because at that level MSI is just a normal DMA write going upstream. The AMD 8131 hypertransport to PCI-X bridge only failed because at the connection to hypertransport it did not implement the hypertransport msi mapping capability and the associated logic to convert an MSI irq into a hypertranposrt IRQ. I currently have a quirk that looks for any hypertransport msi mapping capability and only enables MSI on the downstream bus of the bridge. > Also in the x86 world Microsoft defined a FADT ACPI flag that MSI doesn't > work for Vista. It might make sense to do > > if (dmi year >= 2007 && FADT.msi_disable not set) assume it works Sounds reasonable to me. If it happens to work reliably. >> This patch should be safe. The anecdotal evidence is that when dealing >> with MSI the Intel chipsets just work. If we find some buggy ones >> changing the list won't be hard. > > The FADT bit should be probably checked anyways. Sure if we have a way to check I have no problem, although I tend to trust the hardware more. Eric - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
