[PATCH AUTOSEL for 3.18 26/63] ARM: dts: r8a7790: Correct parent of SSI[0-9] clocks

[Sasha Levin]

From: Geert Uytterhoeven <geert+rene...@glider.be>

[ Upstream commit d13d4e063d4a08eb1686e890e9183dde709871bf ]

The SSI-ALL gate clock is located in between the P clock and the
individual SSI[0-9] clocks, hence the former should be listed as their
parent.

Fixes: bcde372254386872 ("ARM: shmobile: r8a7790: add MSTP10 support on DTSI")
Signed-off-by: Geert Uytterhoeven <geert+rene...@glider.be>
Signed-off-by: Simon Horman <horms+rene...@verge.net.au>
Signed-off-by: Sasha Levin <alexander.le...@microsoft.com>
---
 arch/arm/boot/dts/r8a7790.dtsi | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index e20affe156c1..2a4e54732419 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -978,8 +978,11 @@
                        compatible = "renesas,r8a7790-mstp-clocks", 
"renesas,cpg-mstp-clocks";
                        reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
                        clocks = <&p_clk>,
-                               <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, 
<&p_clk>,
-                               <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, 
<&p_clk>,
+                               <&mstp10_clks R8A7790_CLK_SSI_ALL>, 
<&mstp10_clks R8A7790_CLK_SSI_ALL>,
+                               <&mstp10_clks R8A7790_CLK_SSI_ALL>, 
<&mstp10_clks R8A7790_CLK_SSI_ALL>,
+                               <&mstp10_clks R8A7790_CLK_SSI_ALL>, 
<&mstp10_clks R8A7790_CLK_SSI_ALL>,
+                               <&mstp10_clks R8A7790_CLK_SSI_ALL>, 
<&mstp10_clks R8A7790_CLK_SSI_ALL>,
+                               <&mstp10_clks R8A7790_CLK_SSI_ALL>, 
<&mstp10_clks R8A7790_CLK_SSI_ALL>,
                                <&p_clk>,
                                <&mstp10_clks R8A7790_CLK_SCU_ALL>, 
<&mstp10_clks R8A7790_CLK_SCU_ALL>,
                                <&mstp10_clks R8A7790_CLK_SCU_ALL>, 
<&mstp10_clks R8A7790_CLK_SCU_ALL>,
-- 
2.14.1