On Tue, Mar 6, 2018 at 6:16 AM, Alexandre Belloni <[email protected]> wrote: > Add a device tree include file for the Microsemi Ocelot SoC. > > Cc: Rob Herring <[email protected]> > Cc: [email protected] > Signed-off-by: Alexandre Belloni <[email protected]> > --- > arch/mips/boot/dts/Makefile | 1 + > arch/mips/boot/dts/mscc/Makefile | 1 + > arch/mips/boot/dts/mscc/ocelot.dtsi | 117 > ++++++++++++++++++++++++++++++++++++ > 3 files changed, 119 insertions(+) > create mode 100644 arch/mips/boot/dts/mscc/Makefile > create mode 100644 arch/mips/boot/dts/mscc/ocelot.dtsi > > diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile > index e2c6f131c8eb..1e79cab8e269 100644 > --- a/arch/mips/boot/dts/Makefile > +++ b/arch/mips/boot/dts/Makefile > @@ -4,6 +4,7 @@ subdir-y += cavium-octeon > subdir-y += img > subdir-y += ingenic > subdir-y += lantiq > +subdir-y += mscc > subdir-y += mti > subdir-y += netlogic > subdir-y += ni > diff --git a/arch/mips/boot/dts/mscc/Makefile > b/arch/mips/boot/dts/mscc/Makefile > new file mode 100644 > index 000000000000..dd08e63a10ba > --- /dev/null > +++ b/arch/mips/boot/dts/mscc/Makefile > @@ -0,0 +1 @@ > +obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y)) > diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi > b/arch/mips/boot/dts/mscc/ocelot.dtsi > new file mode 100644 > index 000000000000..8c3210577410 > --- /dev/null > +++ b/arch/mips/boot/dts/mscc/ocelot.dtsi > @@ -0,0 +1,117 @@ > +//SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* Copyright (c) 2017 Microsemi Corporation */ > + > +/ { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "mscc,ocelot"; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu@0 { > + compatible = "mips,mips24KEc"; > + device_type = "cpu"; > + clocks = <&cpu_clk>; > + reg = <0>; > + }; > + }; > + > + aliases { > + serial0 = &uart0; > + }; > + > + cpuintc: interrupt-controller@0 {
Please compile with W=1 and fix any issues like this one which is a unit-address without a reg property. Drop the unit-address. > + #address-cells = <0>; > + #interrupt-cells = <1>; > + interrupt-controller; > + compatible = "mti,cpu-interrupt-controller";
