On Fri, Mar 09, 2018 at 01:44:40PM +0000, Mark Rutland wrote:
> On Wed, Mar 07, 2018 at 09:00:08AM -0600, Shanker Donthineni wrote:
> > static inline void __flush_icache_all(void)
> > {
> > - asm("ic ialluis");
> > - dsb(ish);
> > + /* Instruction cache invalidation is not required for I/D coherence? */
> > + if (!cpus_have_const_cap(ARM64_HAS_CACHE_DIC)) {
> > + asm("ic ialluis");
> > + dsb(ish);
> > + }
> > }
>
> I don't think we need the comment here. We don't have this in the other
> cases we look at the ARM64_HAS_CACHE_{IDC,DIC} caps.
>
> This would also be slightly nicer as an early return:
>
> static inline void __flush_icache_all(void)
> {
> if (cpus_have_const_cap(ARM64_HAS_CACHE_DIC))
> return;
>
> asm("ic ialluis");
> dsb(ish);
> }
>
> ... which minimizes indentation, and the diffstat.
>
> The rest looks fine to me, so with the above changes:
>
> Reviewed-by: Mark Rutland <[email protected]>
I've already queued this, but not pushed out yet so I'll fold these changes
in.
Will
