Reviewed-by: Abhishek Sahu <abs...@codeaurora.org>
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
 arch/arm/boot/dts/Makefile                      |  1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts | 65 +++++++++++++++++++++++++
 2 files changed, 66 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b71487a..8c93fd0 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -749,6 +749,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
        qcom-ipq4019-ap.dk01.1-c1.dtb \
        qcom-ipq4019-ap.dk04.1-c1.dtb \
        qcom-ipq4019-ap.dk04.1-c3.dtb \
+       qcom-ipq4019-ap.dk07.1-c1.dtb \
        qcom-ipq8064-ap148.dtb \
        qcom-msm8660-surf.dtb \
        qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
new file mode 100644
index 0000000..e4fddc1
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk07.1.dtsi"
+
+/ {
+       model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C1";
+
+       soc {
+               pcie0: pci@40000000 {
+                       status = "ok";
+                       perst-gpio = <&tlmm 38 0x1>;
+               };
+
+               spi_1: spi@78b6000 { /* BLSP1 QUP2 */
+                       status = "ok";
+               };
+
+               pinctrl@1000000 {
+                       serial_1_pins: serial1_pinmux {
+                               mux {
+                                       pins = "gpio8", "gpio9",
+                                               "gpio10", "gpio11";
+                                       function = "blsp_uart1";
+                                       bias-disable;
+                               };
+                       };
+
+                       spi_0_pins: spi_0_pinmux {
+                               pinmux {
+                                       function = "blsp_spi0";
+                                       pins = "gpio13", "gpio14", "gpio15";
+                                       bias-disable;
+                               };
+                               pinmux_cs {
+                                       function = "gpio";
+                                       pins = "gpio12";
+                                       bias-disable;
+                                       output-high;
+                               };
+                       };
+               };
+
+               serial@78b0000 {
+                       pinctrl-0 = <&serial_1_pins>;
+                       pinctrl-names = "default";
+                       status = "ok";
+               };
+
+               spi_0: spi@78b5000 { /* BLSP1 QUP1 */
+                       pinctrl-0 = <&spi_0_pins>;
+                       pinctrl-names = "default";
+                       status = "ok";
+                       cs-gpios = <&tlmm 12 0>;
+
+                       m25p80@0 {
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               reg = <0>;
+                               compatible = "n25q128a11";
+                               spi-max-frequency = <24000000>;
+                       };
+               };
+       };
+};
-- 
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