Hi Matt,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on tip/perf/core]
[also build test ERROR on v4.16 next-20180403]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:    
https://github.com/0day-ci/linux/commits/Matt-Redfearn/MIPS-perf-MT-fixes-and-improvements/20180404-011026
config: mips-gpr_defconfig (attached as .config)
compiler: mipsel-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
        wget 
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=mips 

All errors (new ones prefixed by >>):

   arch/mips/kernel/perf_event_mipsxx.c: In function 'mipsxx_pmu_enable_event':
>> arch/mips/kernel/perf_event_mipsxx.c:343:22: error: expected expression 
>> before ')' token
     } else if (range > V) {
                         ^
   arch/mips/kernel/perf_event_mipsxx.c: In function 
'mipspmu_perf_event_encode':
>> arch/mips/kernel/perf_event_mipsxx.c:675:28: error: 'const struct 
>> mips_perf_event' has no member named 'range'
      return ((unsigned int)pev->range << 24) |
                               ^~

vim +343 arch/mips/kernel/perf_event_mipsxx.c

   325  
   326  static void mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx)
   327  {
   328          struct perf_event *event = container_of(evt, struct perf_event, 
hw);
   329          struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
   330          unsigned int range = evt->event_base >> 24;
   331  
   332          WARN_ON(idx < 0 || idx >= mipspmu.num_counters);
   333  
   334          cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0xff) 
|
   335                  (evt->config_base & M_PERFCTL_CONFIG_MASK) |
   336                  /* Make sure interrupt enabled. */
   337                  MIPS_PERFCTRL_IE;
   338  
   339          if (IS_ENABLED(CONFIG_CPU_BMIPS5000)) {
   340                  /* enable the counter for the calling thread */
   341                  cpuc->saved_ctrl[idx] |=
   342                          (1 << (12 + vpe_id())) | BRCM_PERFCTRL_TC;
 > 343          } else if (range > V) {
   344                  /* The counter is processor wide. Set it up to count 
all TCs. */
   345                  pr_debug("Enabling perf counter for all TCs\n");
   346                  cpuc->saved_ctrl[idx] |= M_TC_EN_ALL;
   347          } else {
   348                  unsigned int cpu, ctrl;
   349  
   350                  /*
   351                   * Set up the counter for a particular CPU when 
event->cpu is
   352                   * a valid CPU number. Otherwise set up the counter for 
the CPU
   353                   * scheduling this thread.
   354                   */
   355                  cpu = (event->cpu >= 0) ? event->cpu : 
smp_processor_id();
   356  
   357                  ctrl = M_PERFCTL_VPEID(cpu_vpe_id(&cpu_data[cpu]));
   358                  ctrl |= M_TC_EN_VPE;
   359                  cpuc->saved_ctrl[idx] |= ctrl;
   360                  pr_debug("Enabling perf counter for CPU%d\n", cpu);
   361          }
   362          /*
   363           * We do not actually let the counter run. Leave it until 
start().
   364           */
   365  }
   366  

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

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