Current comment makes not clear the direction of mclk. Previously, similar
description caused a misunderstanding for bclk_master and fsync_master.
This commit solves the potential confusion the same way it is solved for
bclk_master and fsync_master.
Signed-off-by: Kirill Marinushkin <k.marinush...@gmail.com>
Acked-by: Pierre-Louis Bossart <pierre-louis.boss...@linux.intel.com>
Cc: Jaroslav Kysela <pe...@perex.cz>
Cc: Takashi Iwai <ti...@suse.de>
Cc: Mark Brown <broo...@kernel.org>
Cc: Pan Xiuli <xiuli....@linux.intel.com>
Cc: Liam Girdwood <liam.r.girdw...@linux.intel.com>
Cc: linux-kernel@vger.kernel.org
Cc: alsa-de...@alsa-project.org
---
include/uapi/sound/asoc.h | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/include/uapi/sound/asoc.h b/include/uapi/sound/asoc.h
index f3c4b46e39d8..b901cdbe532a 100644
--- a/include/uapi/sound/asoc.h
+++ b/include/uapi/sound/asoc.h
@@ -144,6 +144,10 @@
#define SND_SOC_TPLG_DAI_CLK_GATE_GATED 1
#define SND_SOC_TPLG_DAI_CLK_GATE_CONT 2
+/* DAI mclk_direction */
+#define SND_SOC_TPLG_MCLK_CO 0 /* for codec, mclk is output */
+#define SND_SOC_TPLG_MCLK_CI 1 /* for codec, mclk is input */
+
/* DAI physical PCM data formats.
* Add new formats to the end of the list.
*/
@@ -334,7 +338,7 @@ struct snd_soc_tplg_hw_config {
__u8 invert_fsync; /* 1 for inverted frame clock, 0 for normal */
__u8 bclk_master; /* SND_SOC_TPLG_BCLK_ value */
__u8 fsync_master; /* SND_SOC_TPLG_FSYNC_ value */
- __u8 mclk_direction; /* 0 for input, 1 for output */
+ __u8 mclk_direction; /* SND_SOC_TPLG_MCLK_ value */
__le16 reserved; /* for 32bit alignment */
__le32 mclk_rate; /* MCLK or SYSCLK freqency in Hz */
__le32 bclk_rate; /* BCLK freqency in Hz */
--
2.13.6
