On ST/CZ based platforms, for specific platform bt uart
mux to be defined for bt i2s.
By default, these pins will be used for uart.
After acp reset , it requires to reprogram bt i2s config
mux pins to enable bt i2s instance.
added bt i2s enablement sequence during acp init.

Signed-off-by: Vijendar Mukunda <vijendar.muku...@amd.com>
Signed-off-by: Akshu Agrawal <akshu.agra...@amd.com>
---
 sound/soc/amd/acp-da7219-max98357a.c | 2 ++
 sound/soc/amd/acp-pcm-dma.c          | 9 +++++++++
 sound/soc/amd/acp.h                  | 1 +
 3 files changed, 12 insertions(+)

diff --git a/sound/soc/amd/acp-da7219-max98357a.c 
b/sound/soc/amd/acp-da7219-max98357a.c
index b205c78..6dad0cb 100644
--- a/sound/soc/amd/acp-da7219-max98357a.c
+++ b/sound/soc/amd/acp-da7219-max98357a.c
@@ -44,6 +44,7 @@
 
 static struct snd_soc_jack cz_jack;
 struct clk *da7219_dai_clk;
+extern int bt_pad_enable;
 
 static int cz_da7219_init(struct snd_soc_pcm_runtime *rtd)
 {
@@ -81,6 +82,7 @@ static int cz_da7219_init(struct snd_soc_pcm_runtime *rtd)
        }
 
        da7219_aad_jack_det(component, &cz_jack);
+       bt_pad_enable = device_property_read_bool(&pdev->dev, "bt-pad-enable");
 
        return 0;
 }
diff --git a/sound/soc/amd/acp-pcm-dma.c b/sound/soc/amd/acp-pcm-dma.c
index 7c392fe..b52c660 100644
--- a/sound/soc/amd/acp-pcm-dma.c
+++ b/sound/soc/amd/acp-pcm-dma.c
@@ -46,6 +46,8 @@
 
 #define DRV_NAME "acp_audio_dma"
 
+bool bt_pad_enable = false;
+EXPORT_SYMBOL(bt_pad_enable);
 
 static const struct snd_pcm_hardware acp_pcm_hardware_playback = {
        .info = SNDRV_PCM_INFO_INTERLEAVED |
@@ -525,6 +527,13 @@ static int acp_init(void __iomem *acp_mmio, u32 asic_type)
        val &= ~ACP_SOFT_RESET__SoftResetAud_MASK;
        acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);
 
+       /* For BT instance change pins from UART to BT */
+       if (bt_pad_enable) {
+               val = acp_reg_read(acp_mmio, mmACP_BT_UART_PAD_SEL);
+               val |= ACP_BT_UART_PAD_SELECT_MASK;
+               acp_reg_write(val, acp_mmio, mmACP_BT_UART_PAD_SEL);
+       }
+
        /* initiailize Onion control DAGB register */
        acp_reg_write(ACP_ONION_CNTL_DEFAULT, acp_mmio,
                      mmACP_AXI2DAGB_ONION_CNTL);
diff --git a/sound/soc/amd/acp.h b/sound/soc/amd/acp.h
index 460365c..6b43144 100644
--- a/sound/soc/amd/acp.h
+++ b/sound/soc/amd/acp.h
@@ -107,6 +107,7 @@
 #define ACP_I2S_MIC_16BIT_RESOLUTION_EN 0x01
 #define ACP_I2S_SP_16BIT_RESOLUTION_EN 0x02
 #define ACP_I2S_BT_16BIT_RESOLUTION_EN 0x04
+#define ACP_BT_UART_PAD_SELECT_MASK    0x1
 
 enum acp_dma_priority_level {
        /* 0x0 Specifies the DMA channel is given normal priority */
-- 
2.7.4

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