On Mon, Apr 23, 2018 at 8:48 AM, Peter Zijlstra <pet...@infradead.org> wrote: > On Mon, Apr 23, 2018 at 08:23:24AM -0300, Diego Viola wrote: >> > That's a Core2 era chip; does it actually have stable TSC ? >> >> I'm not sure. > > dmesg | grep -i tsc > > should be able to tell you.
[diego@dualcore ~]$ dmesg | grep -i tsc [ 0.000000] tsc: Fast TSC calibration using PIT [ 0.016666] tsc: Fast TSC calibration using PIT [ 0.019999] tsc: Detected 2793.087 MHz processor [ 0.019999] clocksource: tsc-early: mask: 0xffffffffffffffff max_cycles: 0x2842be30f1f, max_idle_ns: 440795236296 ns [ 0.162058] clocksource: Switched to clocksource tsc-early [ 0.300076] tsc: Marking TSC unstable due to TSC halts in idle [diego@dualcore ~]$
