On 20/04/2018 11:56, Jerome Brunet wrote: > Let the mpll dividers achieve the closest rate possible, even if > it means rounding the requested rate up. > > This is done to improve the accuracy of the rates provided by these > plls to the audio subsystem > > Signed-off-by: Jerome Brunet <[email protected]> > --- > drivers/clk/meson/axg.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c > index 5f5d468c1efe..bd4dbc696b88 100644 > --- a/drivers/clk/meson/axg.c > +++ b/drivers/clk/meson/axg.c > @@ -461,6 +461,7 @@ static struct clk_regmap axg_mpll0_div = { > .width = 1, > }, > .lock = &meson_clk_lock, > + .flags = CLK_MESON_MPLL_ROUND_CLOSEST, > }, > .hw.init = &(struct clk_init_data){ > .name = "mpll0_div", > @@ -507,6 +508,7 @@ static struct clk_regmap axg_mpll1_div = { > .width = 1, > }, > .lock = &meson_clk_lock, > + .flags = CLK_MESON_MPLL_ROUND_CLOSEST, > }, > .hw.init = &(struct clk_init_data){ > .name = "mpll1_div", > @@ -553,6 +555,7 @@ static struct clk_regmap axg_mpll2_div = { > .width = 1, > }, > .lock = &meson_clk_lock, > + .flags = CLK_MESON_MPLL_ROUND_CLOSEST, > }, > .hw.init = &(struct clk_init_data){ > .name = "mpll2_div", > @@ -599,6 +602,7 @@ static struct clk_regmap axg_mpll3_div = { > .width = 1, > }, > .lock = &meson_clk_lock, > + .flags = CLK_MESON_MPLL_ROUND_CLOSEST, > }, > .hw.init = &(struct clk_init_data){ > .name = "mpll3_div", >
Acked-by: Neil Armstrong <[email protected]>
