Hi,
On Mon, Apr 30, 2018 at 05:10:46PM +0530, Jagan Teki wrote:
> + hdmi_phy: hdmi-phy@1ef0000 {
> + compatible = "allwinner,sun50i-a64-hdmi-phy",
> + "allwinner,sun8i-h3-hdmi-phy";
> + reg = <0x01ef0000 0x10000>;
> + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
> + <&ccu CLK_PLL_VIDEO1>;You were discussing that the PLL0 could also be used to clock the PHY, has that been figured out? Thanks! Maxime -- Maxime Ripard, Bootlin (formerly Free Electrons) Embedded Linux and Kernel engineering https://bootlin.com
signature.asc
Description: PGP signature
