Parents of CDEV1/2 clocks are determined by muxing of the corresponding
pins. Pinctrl driver now provides the CDEV1/2 clock muxes and hence
CDEV1/2 clocks could have correct parents. Set CDEV1/2 parents to the
corresponding muxes to fix the parents.
Signed-off-by: Dmitry Osipenko <dig...@gmail.com>
Reviewed-by: Marcel Ziswiler <mar...@ziswiler.com>
Tested-by: Marcel Ziswiler <mar...@ziswiler.com>
Tested-by: Marc Dietrich <marvi...@gmx.de>
Acked-by: Peter De Schrijver <pdeschrij...@nvidia.com>
Acked-by: Stephen Boyd <sb...@kernel.org>
---
drivers/clk/tegra/clk-tegra20.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index ad5a7b5e3a39..636500a98561 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -846,14 +846,12 @@ static void __init tegra20_periph_clk_init(void)
NULL);
/* cdev1 */
- clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, 0, 26000000);
- clk = tegra_clk_register_periph_gate("cdev1", "cdev1_fixed", 0,
+ clk = tegra_clk_register_periph_gate("cdev1", "cdev1_mux", 0,
clk_base, 0, 94, periph_clk_enb_refcnt);
clks[TEGRA20_CLK_CDEV1] = clk;
/* cdev2 */
- clk = clk_register_fixed_rate(NULL, "cdev2_fixed", NULL, 0, 26000000);
- clk = tegra_clk_register_periph_gate("cdev2", "cdev2_fixed", 0,
+ clk = tegra_clk_register_periph_gate("cdev2", "cdev2_mux", 0,
clk_base, 0, 93, periph_clk_enb_refcnt);
clks[TEGRA20_CLK_CDEV2] = clk;
--
2.17.0
