4.16-stable review patch. If anyone has any objections, please let me know.
------------------ From: Jerome Brunet <[email protected]> [ Upstream commit 6b71aceceb09918daf37a40a1221077599040be3 ] The fixed_pll also has a fractional part. On axg s400 board, without this parameter, the calculated rate is off by ~8Mhz (0,4%). The fixed_pll being the root of the peripheral clock tree, this error is propagated to the rest of the clocks Adding the definition of the parameter fixes the problem Fixes: 78b4af312f91 ("clk: meson-axg: add clock controller drivers") Signed-off-by: Jerome Brunet <[email protected]> Signed-off-by: Sasha Levin <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]> --- drivers/clk/meson/axg.c | 5 +++++ 1 file changed, 5 insertions(+) --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -129,6 +129,11 @@ static struct meson_clk_pll axg_fixed_pl .shift = 16, .width = 2, }, + .frac = { + .reg_off = HHI_MPLL_CNTL2, + .shift = 0, + .width = 12, + }, .lock = &meson_clk_lock, .hw.init = &(struct clk_init_data){ .name = "fixed_pll",
