On Mon, Jun 04, 2018 at 01:36:49AM +0300, Dmitry Osipenko wrote: > Hello, > > Couple years ago the Tegra20 EMC driver was removed from the kernel > due to incompatible changes in the Tegra's clock driver. This patchset > introduces a modernized EMC driver. Currently the sole purpose of the > driver is to initialize DRAM frequency to maximum rate during of the > kernels boot-up. Later we may consider implementing dynamic memory > frequency scaling, utilizing functionality provided by this driver. > > Changelog: > > v2: > - Minor code cleanups like consistent use of writel_relaxed instead > of non-relaxed version, reworded error messages, etc. > > - Factored out use_pllm_ud bit checking into a standalone patch for > consistency. > > Dmitry Osipenko (5): > dt: bindings: tegra20-emc: Document interrupt property > ARM: dts: tegra20: Add interrupt to External Memory Controller > clk: tegra20: Turn EMC clock gate into divider > clk: tegra20: Check whether direct PLLM sourcing is turned off for EMC > memory: tegra: Introduce Tegra20 EMC driver
I took a brief look and didn't spot any dependencies between the clk and memory patches. Is it correct that these can be applied separately? Thierry
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