Hi, Peter and Paul,
Loongson-3's Store Fill Buffer is nearly the same as your "Store Buffer", and
it increases the memory ordering weakness. So, smp_cond_load_acquire() only
need a __smp_mb() before the loop, not after every READ_ONCE(). In other word,
the following code is just OK:
#define smp_cond_load_acquire(ptr, cond_expr) \
({ \
typeof(ptr) __PTR = (ptr); \
typeof(*ptr) VAL; \
__smp_mb(); \
for (;;) { \
VAL = READ_ONCE(*__PTR); \
if (cond_expr) \
break; \
cpu_relax(); \
} \
__smp_mb(); \
VAL; \
})
the __smp_mb() before loop is used to avoid "reads prioritised over writes",
which is caused by SFB's weak ordering and similar to ARM11MPCore (mentioned by
Will Deacon).
Huacai
------------------ Original ------------------
From: "Peter Zijlstra"<pet...@infradead.org>;
Date: Tue, Jun 19, 2018 03:22 PM
To: "陈华才"<che...@lemote.com>;
Cc: "Paul Burton"<paul.bur...@mips.com>; "Ralf Baechle"<r...@linux-mips.org>;
"James Hogan"<james.ho...@mips.com>; "linux-mips"<linux-m...@linux-mips.org>;
"Fuxin Zhang"<zhan...@lemote.com>; "wuzhangjin"<wuzhang...@gmail.com>; "Huacai
Chen"<chenhua...@gmail.com>; "stable"<sta...@vger.kernel.org>; "Alan
Stern"<st...@rowland.harvard.edu>;
"AndreaParri"<andrea.pa...@amarulasolutions.com>; "Will
Deacon"<will.dea...@arm.com>; "Boqun Feng"<boqun.f...@gmail.com>; "Nicholas
Piggin"<npig...@gmail.com>; "David Howells"<dhowe...@redhat.com>; "Jade
Alglave"<j.algl...@ucl.ac.uk>; "Luc Maranget"<luc.maran...@inria.fr>; "Paul E.
McKenney"<paul...@linux.vnet.ibm.com>; "Akira Yokosawa"<aki...@gmail.com>;
"linux-kernel"<linux-kernel@vger.kernel.org>;
Subject: Re: [PATCH] MIPS: implement smp_cond_load_acquire() for Loongson-3
On Tue, Jun 19, 2018 at 02:40:14PM +0800, 陈华才 wrote:
> Hi, Paul,
>
> First of all, could you please check why linux-mips reject e-mails
> from lemote.com? Of course I can send e-mails by gmail, but my gmail
> can't receive e-mails from linux-mips since March, 2018.
Could you please learn to use email? No top posting and wrap lines at 78
chars.
> I have already read Documentation/memory-barriers.txt, but I don't
> think we should define a smp_read_barrier_depends() for Loongson-3.
> Because Loongson-3's behavior isn't like Alpha, and in syntax, this is
> not a data-dependent issue.
Agreed, this is not a data-dependency issue.
> There is no document about Loongson-3's SFB. In my opinion, SFB looks
> like the L0 cache but sometimes it is out of cache-coherent machanism
> (L1 cache's cross-core coherency is maintained by hardware, but not
> always true for SFB). smp_mb() is needed for smp_cond_load_acquire(),
> but not every READ_ONCE().
Linux does _NOT_ support non-coherent SMP. If your system is not fully
coherent, you're out of luck.
But please, explain in excruciating detail what exactly you need that
smp_mb for. If, like I posited in my previous email, it is to ensure
remote store buffer flushes, then your machine is terminally broken.
