On Tue, 19 Jun 2018 11:07:41 +0200
Miquel Raynal <miquel.ray...@bootlin.com> wrote:
> On Mon, 18 Jun 2018 22:41:03 +0200, Martin Kaiser <mar...@kaiser.cx>
> wrote:
>
> > The v21 version of the NAND flash controller contains a Spare Area Size
> > Register (SPAS) at offset 0x10. Its setting defaults to the maximum
> > spare area size of 218 bytes. The size that is set in this register is
> > used by the controller when it calculates the ECC bytes internally in
> > hardware.
> >
> > Usually, this register is updated from settings in the IIM fuses when
> > the system is booting from NAND flash. For other boot media, however,
> > the SPAS register remains at the default setting, which may not work for
> > the particular flash chip on the board. The same goes for flash chips
> > whose configuration cannot be set in the IIM fuses (e.g. chips with 2k
> > sector size and 128 bytes spare area size can't be configured in the IIM
> > fuses on imx25 systems).
> >
> > Set the SPAS register explicitly during the preset operation. Derive the
> > register value from mtd->oobsize that was detected during probe by
> > decoding the flash chip's ID bytes.
> >
> > While at it, rename the define for the spare area register's offset to
> > NFC_V21_RSLTSPARE_AREA. The register at offset 0x10 on v1 controllers is
> > different from the register on v21 controllers.
> >
> > Signed-off-by: Martin Kaiser <mar...@kaiser.cx>
> > Cc: sta...@vger.kernel.org
> > Fixes: d484018 ("mtd: mxc_nand: set NFC registers after reset")
>
> Reviewed-by: Miquel Raynal <miquel.ray...@bootlin.com>
Applied.
Thanks,
Boris
