On Fri, 2018-06-22 at 10:05 -0700, Dave Hansen wrote: > On 06/20/2018 12:56 PM, Rik van Riel wrote: > > This patch deals with that issue by introducing a third TLB state, > > TLBSTATE_FLUSH, which causes %CR3 to be reloaded at the next > > context > > switch. > > With PCIDs, do we need to be a bit more explicit about what kind of > %CR3 > reload we have? Because, with PCIDs, we do have non-TLB-flushing > %CR3 > writes.
Probably not in this patch series, because switch_mm_irqs_off
calls choose_new_asid, which figures all of this out for us
already.
Specifically, it has this bit of code to figure out whether
we need a flush:
*need_flush =
(this_cpu_read(cpu_tlbstate.ctxs[asid].tlb_gen) <
next_tlb_gen);
As long as we get the memory ordering right, we should be
able to rely on that to switch back from lazy to non-lazy
TLB mode.
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