On Wed, Jul 11, 2018 at 11:21:06AM +0100, Will Deacon wrote: > On Wed, Jul 11, 2018 at 06:05:51PM +0800, Jiaxun Yang wrote: > > On 2018-7-10 Tue at 20:17:27，Peter Zijlstra Wrote：
> > > Still, even with the rules above, the best work-around is still the very > > > same cpu_relax() hack. > > > > As you say, SFB makes Loongson not fully SMP-coherent. > > However, modify cpu_relax can solve the current problem, > > but not so straight forward. On the other hand, providing a > > Loongson-specific > > WRITE_ONCE looks more reasonable, because it the eliminate the > > "non-cohrency". > > So we can solve the bug from the root. > > Curious, but why is it not straight-forward to hack cpu_relax()? If you try > to hack WRITE_ONCE, you also need to hack atomic_set, atomic64_set and all > the places that should be using WRITE_ONCE but aren't ;~) Right. The problem isn't stores pre-se, normal progress should contain enough stores to flush out 'old' bits in the natural order of things. But the problem is spin-wait loops that inhibit normal progress (and thereby store-buffer flushing). And all spin-wait loops should be having cpu_relax() in them. So cpu_relax() is the natural place to fix this. Adding SYNC to WRITE_ONCE()/atomic* will hurt performance lots and will ultimately not guarantee anything more; and as Will said, keep you chasing dragons where people forgot to use WRITE_ONCE() where they maybe should've.
