On Wed, 2018-07-11 at 21:41 +0800, Jian Hu wrote:
> > > > > +static struct clk_regmap g12a_mpll0 = {
> > > > > + .data = &(struct clk_regmap_gate_data){
> > > > > + .offset = HHI_MPLL_CNTL1,
> > > > > + .bit_idx = 31,
> > > > > + },
> > > > > + .hw.init = &(struct clk_init_data){
> > > > > + .name = "mpll0",
> > > > > + .ops = &clk_regmap_gate_ops,
> > > > > + .parent_names = (const char *[]){ "mpll0_div" },
> > > > > + .num_parents = 1,
> > > > > + .flags = CLK_SET_RATE_PARENT,
> > > > > + },
> > > > > +};
> >
> > The previous had a predivider (1 or 2) in front of these mpll. Even if the
> > predivider is usually set to be a passthrough, it is better to model the
> > tree
> > correctly.
> >
> > Is this SoC any different ?
> >
>
> I am not sure the difference, I will confirm with IC design guys.
I suggest that you have a look at the (upstream) axg and gxbb clock driver for
this
Same goes for the fdiv gates.
Last, please trim your replies a bit. It will make easier to see what you are
replying to.
