Instead of relying on default values, configure PAD_AUD3_BB_CK to be a GPIO explicitly. While at, it change the pad configuration to enable a 100K pull-down (the pin is used as IRQ_TYPE_LEVEL_HIGH).
Cc: Fabio Estevam <[email protected]> Cc: Nikita Yushchenko <[email protected]> Cc: Lucas Stach <[email protected]> Cc: [email protected] Cc: Shawn Guo <[email protected]> Cc: Rob Herring <[email protected]> Cc: Mark Rutland <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: Andrew Lunn <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: Andrey Smirnov <[email protected]> --- arch/arm/boot/dts/imx51-zii-scu3-esb.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/imx51-zii-scu3-esb.dts b/arch/arm/boot/dts/imx51-zii-scu3-esb.dts index 2941a92d40f1..0bb42c00d72b 100644 --- a/arch/arm/boot/dts/imx51-zii-scu3-esb.dts +++ b/arch/arm/boot/dts/imx51-zii-scu3-esb.dts @@ -221,6 +221,8 @@ interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_switch>; ports { #address-cells = <1>; @@ -426,6 +428,12 @@ >; }; + pinctrl_switch: switchgrp { + fsl,pins = < + MX51_PAD_AUD3_BB_CK__GPIO4_20 0xc5 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 -- 2.17.1
