Il 18/07/2018 11:22, Giulio Benetti ha scritto:
+#define M41TXX_REG_CONTROL 0x07 +# define M41TXX_BIT_OUT BIT(7) +# define M41TXX_BIT_FT BIT(6) +# define M41TXX_BIT_CALIB_SIGN BIT(5) +# define M41TXX_M_CALIBRATION GENMASK(5, 0)
This must be GENMASK(4, 0) to be 0x1f. I'm going to send last patchset, sorry everyone for the mess. Giulio
