A clock controller could be connected to single or multiple power domains. Add support for powerdomain_class which would help associate these power domains to the RCGs and PLLs in the clock controller. Map the domain and the corresponding frequencies to the clock(RCG/PLL). The clock frequency request from a consumer would be mapped to the corresponding performance corner, aggregated at the clock driver and would be vote/unvoted to the genpd framework for the desired performance state.
This series add an example of power domain class for sdm845 RCG/PLLs and the corresponding frequency mappings. This depends on power domain drivers of SDM845 https://lkml.org/lkml/2018/6/27/7. Taniya Das (4): clk: qcom: Add support to request power domain state clk: qcom: Initialize the power domain class for each clock clk: qcom: Add prepare/unprepare clock ops for PLL/RCG clk: qcom: sdm845: Add Power Domain to RCGs and PLL arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-alpha-pll.c | 52 ++++++++-- drivers/clk/qcom/clk-pd.c | 193 +++++++++++++++++++++++++++++++++++ drivers/clk/qcom/clk-pd.h | 55 ++++++++++ drivers/clk/qcom/clk-rcg2.c | 61 +++++++++-- drivers/clk/qcom/clk-regmap.h | 5 + drivers/clk/qcom/common.c | 17 ++- drivers/clk/qcom/gcc-sdm845.c | 83 ++++++++++++--- 9 files changed, 427 insertions(+), 42 deletions(-) create mode 100644 drivers/clk/qcom/clk-pd.c create mode 100644 drivers/clk/qcom/clk-pd.h -- Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.
