On 25/07/2018 14:22:41+0200, Quentin Schulz wrote:
> There is an additional MIIM (MDIO) bus in this SoC so let's declare it
> in the dtsi.
>
> This bus requires GPIO 14 and 15 pins that need to be muxed. There is no
> support for internal PHY reset on this bus on the contrary of MIIM0 so
> there is only one register address space and not two.
>
> Signed-off-by: Quentin Schulz <quentin.sch...@bootlin.com>
Acked-by: Alexandre Belloni <alexandre.bell...@bootlin.com>
> ---
> arch/mips/boot/dts/mscc/ocelot.dtsi | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi
> b/arch/mips/boot/dts/mscc/ocelot.dtsi
> index 7096915f26e0..d7f0e3551500 100644
> --- a/arch/mips/boot/dts/mscc/ocelot.dtsi
> +++ b/arch/mips/boot/dts/mscc/ocelot.dtsi
> @@ -178,6 +178,11 @@
> pins = "GPIO_12", "GPIO_13";
> function = "uart2";
> };
> +
> + miim1: miim1 {
> + pins = "GPIO_14", "GPIO_15";
> + function = "miim1";
> + };
> };
>
> mdio0: mdio@107009c {
> @@ -201,5 +206,16 @@
> reg = <3>;
> };
> };
> +
> + mdio1: mdio@10700c0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "mscc,ocelot-miim";
> + reg = <0x10700c0 0x24>;
> + interrupts = <15>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&miim1>;
> + status = "disabled";
> + };
> };
> };
> --
> 2.14.1
>
--
Alexandre Belloni, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
