Quoting Stephen Boyd (2018-07-27 09:41:40) > Quoting Yixun Lan (2018-07-27 07:52:23) > > HI Stephen: > > > > On 07/26/2018 11:20 PM, Stephen Boyd wrote: > > > Quoting Yixun Lan (2018-07-12 14:12:44) > > >> diff --git a/drivers/clk/meson/mmc-clkc.c b/drivers/clk/meson/mmc-clkc.c > > >> new file mode 100644 > > >> index 000000000000..36c4c7cd69a6 > > >> --- /dev/null > > >> +++ b/drivers/clk/meson/mmc-clkc.c > > >> @@ -0,0 +1,367 @@ > > >> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > > >> +/* > > >> + * Amlogic Meson MMC Sub Clock Controller Driver > > >> + * > > >> + * Copyright (c) 2017 Baylibre SAS. > > >> + * Author: Jerome Brunet <jbru...@baylibre.com> > > >> + * > > >> + * Copyright (c) 2018 Amlogic, inc. > > >> + * Author: Yixun Lan <yixun....@amlogic.com> > > >> + */ > > >> + > > >> +#include <linux/clk.h> > > > > > > Is this include used? > > > > > this is needed by clk_get_rate() > > see drivers/clk/meson/mmc-clkc.c:204 > > Hmm ok. That's unfortunate.
You should be able to read the hardware to figure out the clk frequency? This may be a sign that the phase clk_ops are bad and should be passing in the frequency of the parent clk to the op so that phase can be calculated. Jerome?