[PATCH] perf/x86/intel: Add support for MISPREDICT bit on Knights Landing cpus

[Jacek Tomaka]

From: Jacek Tomaka <jac...@dugeo.com>

Knights Landing supports half baked LBR_FORMAT_TIME format. The addresses are 
linear but it does have MISPREDICT bit but nothing else.
Unfortunately IA32_PERF_CAPABILITIES[5:0] will report LBR_FORMAT_LIP. This 
change teaches LBR about this Knights Landing quirk.
---
 arch/x86/events/intel/lbr.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
index cf372b9055..0f73e60315 100644
--- a/arch/x86/events/intel/lbr.c
+++ b/arch/x86/events/intel/lbr.c
@@ -1230,4 +1230,10 @@ void intel_pmu_lbr_init_knl(void)
 
        x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
        x86_pmu.lbr_sel_map  = snb_lbr_sel_map;
+
+       /* Knights Landing supports half baked LBR format. The addresses are 
linear but it does have MISPREDICT bit.
+        * Unfortunately IA32_PERF_CAPABILITIES[5:0] will report LBR_FORMAT_LIP.
+        */
+       if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_LIP)
+               lbr_desc[LBR_FORMAT_LIP] |= LBR_EIP_FLAGS;
 }
-- 
2.17.0