From: Marcel Ziswiler <[email protected]> This is similar to tegra124 and avoids the following being reported upon boot:
hw perfevents: no interrupt-affinity property for /pmu, guessing. Signed-off-by: Marcel Ziswiler <[email protected]> Reviewed-by: Stefan Agner <[email protected]> --- Changes in v2: - Add Stefan's acks. arch/arm/boot/dts/tegra20.dtsi | 2 ++ arch/arm/boot/dts/tegra30.dtsi | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index a22c6a8f8f83..dcad6d6128cf 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -867,5 +867,7 @@ compatible = "arm,cortex-a9-pmu"; interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&{/cpus/cpu@0}>, + <&{/cpus/cpu@1}>; }; }; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index a6781f653310..1de10f0d1da7 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -1013,5 +1013,9 @@ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&{/cpus/cpu@0}>, + <&{/cpus/cpu@1}>, + <&{/cpus/cpu@2}>, + <&{/cpus/cpu@3}>; }; }; -- 2.14.4
