Ping. > -----Original Message----- > From: Manish Narani [mailto:[email protected]] > Sent: Saturday, August 4, 2018 2:56 PM > To: [email protected]; [email protected]; [email protected]; > [email protected]; Michal Simek <[email protected]>; [email protected]; > [email protected]; [email protected]; Edgar Iglesias <[email protected]>; > Shubhrajyoti Datta <[email protected]>; Naga Sureshkumar Relli > <[email protected]>; Bharat Kumar Gogada <[email protected]>; > [email protected] > Cc: Srinivas Goud <[email protected]>; Anirudha Sarangi > <[email protected]>; [email protected]; > [email protected]; [email protected]; linux- > [email protected]; Manish Narani <[email protected]> > Subject: [PATCH v4 4/4] arm64: zynqmp: Add DDRC node > > This patch adds ddrc memory controller node in dts. The size mentioned in dts > is 0x30000, because we need to access DDR_QOS INTR registers located at > fd090208 from this driver. > > Signed-off-by: Manish Narani <[email protected]> > --- > arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > index a091e6f..7d6a3cf 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > @@ -355,6 +355,13 @@ > xlnx,bus-width = <64>; > }; > > + mc: memory-controller@fd070000 { > + compatible = "xlnx,zynqmp-ddrc-2.40a"; > + reg = <0x0 0xfd070000 0x0 0x30000>; > + interrupt-parent = <&gic>; > + interrupts = <0 112 4>; > + }; > + > gem0: ethernet@ff0b0000 { > compatible = "cdns,zynqmp-gem", "cdns,gem"; > status = "disabled"; > -- > 2.1.1
