Tested on a i.MX51 platform with rev 2.4 PMIC silicon.  System reboots
without the patch.  System works correctly with the patch in place and
reports a sane temperature.

Tested-by: Chris Healy <cphe...@gmail.com>
On Tue, Aug 28, 2018 at 1:02 PM Fabio Estevam <feste...@gmail.com> wrote:
>
> From: Fabio Estevam <fabio.este...@nxp.com>
>
> When trying to read any MC13892 ADC channel on a imx51-babbage board:
>
> # cat /sys/class/hwmon/hwmon0/device/in7_input
>
> The MC13892 PMIC shutdowns completely.
>
> After debugging this issue and comparing the MC13892 and MC13783
> initializations done in the vendor kernel, it was noticed that the
> CHRGRAWDIV bit of the ADC0 register was not being set.
>
> This bit is set by default after power on, but the driver was
> clearing it.
>
> After setting this bit it is possible to read the ADC values correctly.
>
> Signed-off-by: Fabio Estevam <fabio.este...@nxp.com>
> ---
>  drivers/mfd/mc13xxx-core.c  | 3 ++-
>  include/linux/mfd/mc13xxx.h | 1 +
>  2 files changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mfd/mc13xxx-core.c b/drivers/mfd/mc13xxx-core.c
> index c63e331..f475e84 100644
> --- a/drivers/mfd/mc13xxx-core.c
> +++ b/drivers/mfd/mc13xxx-core.c
> @@ -276,7 +276,8 @@ int mc13xxx_adc_do_conversion(struct mc13xxx *mc13xxx, 
> unsigned int mode,
>
>         mc13xxx_reg_read(mc13xxx, MC13XXX_ADC0, &old_adc0);
>
> -       adc0 = MC13XXX_ADC0_ADINC1 | MC13XXX_ADC0_ADINC2;
> +       adc0 = MC13XXX_ADC0_ADINC1 | MC13XXX_ADC0_ADINC2 |
> +              MC13XXX_ADC0_CHRGRAWDIV;
>         adc1 = MC13XXX_ADC1_ADEN | MC13XXX_ADC1_ADTRIGIGN | MC13XXX_ADC1_ASC;
>
>         /*
> diff --git a/include/linux/mfd/mc13xxx.h b/include/linux/mfd/mc13xxx.h
> index 54a3cd8..2ad9bdc 100644
> --- a/include/linux/mfd/mc13xxx.h
> +++ b/include/linux/mfd/mc13xxx.h
> @@ -249,6 +249,7 @@ struct mc13xxx_platform_data {
>  #define MC13XXX_ADC0_TSMOD0            (1 << 12)
>  #define MC13XXX_ADC0_TSMOD1            (1 << 13)
>  #define MC13XXX_ADC0_TSMOD2            (1 << 14)
> +#define MC13XXX_ADC0_CHRGRAWDIV                (1 << 15)
>  #define MC13XXX_ADC0_ADINC1            (1 << 16)
>  #define MC13XXX_ADC0_ADINC2            (1 << 17)
>
> --
> 2.7.4
>

Reply via email to