Hi,
On Tue, Sep 4, 2018 at 9:41 PM Wolfram Sang <w...@the-dreams.de> wrote: > > On Mon, Sep 03, 2018 at 03:11:11PM +0530, shubhrajyoti.da...@gmail.com wrote: > > From: Shubhrajyoti Datta <shubhrajyoti.da...@xilinx.com> > > > > Disable interrupts while configuring the transfer and enable them back. > > > > We have below as the programming sequence > > 1. start and slave address > > 2. byte count and stop > > > > In some customer platform there was a lot of interrupts between 1 and 2 > > and after slave address (around 7 clock cyles) if 2 is not executed > > then the transaction is nacked. > > > > To fix this case make the 2 writes atomic. > > > > Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.da...@xilinx.com> > > Signed-off-by: Michal Simek <michal.si...@xilinx.com> > > I assume simply changing the order of the register writes won't fix it? No that is not possible. > > I also assume this is stable material? > Yes let me know if you want me to resend with the stable tag?
