4.14-stable review patch. If anyone has any objections, please let me know.
------------------
From: Rex Zhu <rex....@amd.com>
commit 2d227ec2c11c568910299e8f913bac2dda47397c upstream.
DIDTConfig_Polaris12[] table missed a big chunk of data.
Pointed by aidan.fabius <aidan.fab...@coreavi.com>
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
Signed-off-by: Rex Zhu <rex....@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
Cc: sta...@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gre...@linuxfoundation.org>
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c | 43 +++++++++++++++++++
1 file changed, 43 insertions(+)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
@@ -403,6 +403,49 @@ static const struct gpu_pt_config_reg DI
{ ixDIDT_SQ_CTRL1, DIDT_SQ_CTRL1__MAX_POWER_MASK,
DIDT_SQ_CTRL1__MAX_POWER__SHIFT, 0xffff,
GPU_CONFIGREG_DIDT_IND },
{ ixDIDT_SQ_CTRL_OCP, DIDT_SQ_CTRL_OCP__UNUSED_0_MASK,
DIDT_SQ_CTRL_OCP__UNUSED_0__SHIFT, 0x0000,
GPU_CONFIGREG_DIDT_IND },
+ { ixDIDT_SQ_CTRL_OCP,
DIDT_SQ_CTRL_OCP__OCP_MAX_POWER_MASK,
DIDT_SQ_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0xffff,
GPU_CONFIGREG_DIDT_IND },
+
+ { ixDIDT_SQ_CTRL2,
DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK,
DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3853,
GPU_CONFIGREG_DIDT_IND },
+ { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_0_MASK,
DIDT_SQ_CTRL2__UNUSED_0__SHIFT, 0x0000,
GPU_CONFIGREG_DIDT_IND },
+ { ixDIDT_SQ_CTRL2,
DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK,
DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x005a,
GPU_CONFIGREG_DIDT_IND },
+ { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_1_MASK,
DIDT_SQ_CTRL2__UNUSED_1__SHIFT, 0x0000,
GPU_CONFIGREG_DIDT_IND },
+ { ixDIDT_SQ_CTRL2,
DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK,
DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000,
GPU_CONFIGREG_DIDT_IND },
+ { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_2_MASK,
DIDT_SQ_CTRL2__UNUSED_2__SHIFT, 0x0000,
GPU_CONFIGREG_DIDT_IND },
+
+ { ixDIDT_SQ_STALL_CTRL,
DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK,
DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x0001,
GPU_CONFIGREG_DIDT_IND },
+ { ixDIDT_SQ_STALL_CTRL,
DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK,
DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001,
GPU_CONFIGREG_DIDT_IND },
+ { ixDIDT_SQ_STALL_CTRL,
DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK,
DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001,
GPU_CONFIGREG_DIDT_IND },
+ { ixDIDT_SQ_STALL_CTRL,
DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK,
DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT, 0x0ebb,
GPU_CONFIGREG_DIDT_IND },
+ { ixDIDT_SQ_STALL_CTRL,
DIDT_SQ_STALL_CTRL__UNUSED_0_MASK,
DIDT_SQ_STALL_CTRL__UNUSED_0__SHIFT, 0x0000,
GPU_CONFIGREG_DIDT_IND },
+
+ { ixDIDT_SQ_TUNING_CTRL,
DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK,
DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, 0x0001,
GPU_CONFIGREG_DIDT_IND },
+ { ixDIDT_SQ_TUNING_CTRL,
DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK,
DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3853,
GPU_CONFIGREG_DIDT_IND },
+ { ixDIDT_SQ_TUNING_CTRL,
DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK,
DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3153,
GPU_CONFIGREG_DIDT_IND },
+ { ixDIDT_SQ_TUNING_CTRL,
DIDT_SQ_TUNING_CTRL__UNUSED_0_MASK,
DIDT_SQ_TUNING_CTRL__UNUSED_0__SHIFT, 0x0000,
GPU_CONFIGREG_DIDT_IND },
+
+ { ixDIDT_SQ_CTRL0,
DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK,
DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0001,
GPU_CONFIGREG_DIDT_IND },
+ { ixDIDT_SQ_CTRL0,
DIDT_SQ_CTRL0__USE_REF_CLOCK_MASK,
DIDT_SQ_CTRL0__USE_REF_CLOCK__SHIFT, 0x0000,
GPU_CONFIGREG_DIDT_IND },
+ { ixDIDT_SQ_CTRL0,
DIDT_SQ_CTRL0__PHASE_OFFSET_MASK,
DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT, 0x0000,
GPU_CONFIGREG_DIDT_IND },
+ { ixDIDT_SQ_CTRL0,
DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK,
DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000,
GPU_CONFIGREG_DIDT_IND },
+ { ixDIDT_SQ_CTRL0,
DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK,
DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000,
GPU_CONFIGREG_DIDT_IND },
+ { ixDIDT_SQ_CTRL0,
DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK,
DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x0010,
GPU_CONFIGREG_DIDT_IND },
+ { ixDIDT_SQ_CTRL0,
DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK,
DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x0010,
GPU_CONFIGREG_DIDT_IND },
+ { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__UNUSED_0_MASK,
DIDT_SQ_CTRL0__UNUSED_0__SHIFT, 0x0000,
GPU_CONFIGREG_DIDT_IND },
+
+ { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT0_MASK,
DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT, 0x000a,
GPU_CONFIGREG_DIDT_IND },
+ { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT1_MASK,
DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT, 0x0010,
GPU_CONFIGREG_DIDT_IND },
+ { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT2_MASK,
DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT, 0x0017,
GPU_CONFIGREG_DIDT_IND },
+ { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT3_MASK,
DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT, 0x002f,
GPU_CONFIGREG_DIDT_IND },
+
+ { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT4_MASK,
DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT, 0x0046,
GPU_CONFIGREG_DIDT_IND },
+ { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT5_MASK,
DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT, 0x005d,
GPU_CONFIGREG_DIDT_IND },
+ { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT6_MASK,
DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT, 0x0000,
GPU_CONFIGREG_DIDT_IND },
+ { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT7_MASK,
DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT, 0x0000,
GPU_CONFIGREG_DIDT_IND },
+
+ { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MIN_POWER_MASK,
DIDT_TD_CTRL1__MIN_POWER__SHIFT, 0x0000,
GPU_CONFIGREG_DIDT_IND },
+ { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MAX_POWER_MASK,
DIDT_TD_CTRL1__MAX_POWER__SHIFT, 0xffff,
GPU_CONFIGREG_DIDT_IND },
+
+ { ixDIDT_TD_CTRL_OCP, DIDT_TD_CTRL_OCP__UNUSED_0_MASK,
DIDT_TD_CTRL_OCP__UNUSED_0__SHIFT, 0x0000,
GPU_CONFIGREG_DIDT_IND },
{ ixDIDT_TD_CTRL_OCP,
DIDT_TD_CTRL_OCP__OCP_MAX_POWER_MASK,
DIDT_TD_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0x00ff,
GPU_CONFIGREG_DIDT_IND },
{ ixDIDT_TD_CTRL2,
DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK,
DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3fff,
GPU_CONFIGREG_DIDT_IND },
