Commit-ID: 7904ba8a66f400182a204893c92098994e22a88d Gitweb: https://git.kernel.org/tip/7904ba8a66f400182a204893c92098994e22a88d Author: Peter Zijlstra <pet...@infradead.org> AuthorDate: Wed, 19 Sep 2018 10:50:24 +0200 Committer: Thomas Gleixner <t...@linutronix.de> CommitDate: Thu, 27 Sep 2018 20:39:42 +0200
x86/mm/cpa: Optimize __cpa_flush_range() If we IPI for WBINDV, then we might as well kill the entire TLB too. But if we don't have to invalidate cache, there is no reason not to use a range TLB flush. Signed-off-by: Peter Zijlstra (Intel) <pet...@infradead.org> Signed-off-by: Thomas Gleixner <t...@linutronix.de> Reviewed-by: Dave Hansen <dave.han...@intel.com> Cc: Bin Yang <bin.y...@intel.com> Cc: Mark Gross <mark.gr...@intel.com> Link: https://lkml.kernel.org/r/20180919085948.195633...@infradead.org --- arch/x86/mm/pageattr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/mm/pageattr.c b/arch/x86/mm/pageattr.c index dc552824e86a..62bb30b4bd2a 100644 --- a/arch/x86/mm/pageattr.c +++ b/arch/x86/mm/pageattr.c @@ -291,7 +291,7 @@ static bool __cpa_flush_range(unsigned long start, int numpages, int cache) WARN_ON(PAGE_ALIGN(start) != start); - if (!static_cpu_has(X86_FEATURE_CLFLUSH)) { + if (cache && !static_cpu_has(X86_FEATURE_CLFLUSH)) { cpa_flush_all(cache); return true; }
