3.16.59-rc1 review patch. If anyone has any objections, please let me know.
------------------ From: Konrad Rzeszutek Wilk <konrad.w...@oracle.com> commit 0cc5fa00b0a88dad140b4e5c2cead9951ad36822 upstream. Add the CPU feature bit CPUID.7.0.EDX[31] which indicates whether the CPU supports Reduced Data Speculation. [ tglx: Split it out from a later patch ] Signed-off-by: Konrad Rzeszutek Wilk <konrad.w...@oracle.com> Signed-off-by: Thomas Gleixner <t...@linutronix.de> Reviewed-by: Ingo Molnar <mi...@kernel.org> [bwh: Backported to 3.16: - This CPUID word is feature word 10 - Adjust filename] Signed-off-by: Ben Hutchings <b...@decadent.org.uk> --- arch/x86/include/asm/cpufeature.h | 1 + 1 file changed, 1 insertion(+) --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -241,6 +241,7 @@ #define X86_FEATURE_SPEC_CTRL (10*32+26) /* "" Speculation Control (IBRS + IBPB) */ #define X86_FEATURE_INTEL_STIBP (10*32+27) /* "" Single Thread Indirect Branch Predictors */ #define X86_FEATURE_ARCH_CAPABILITIES (10*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */ +#define X86_FEATURE_RDS (10*32+31) /* Reduced Data Speculation */ /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 11 */ #define X86_FEATURE_IBPB (11*32+12) /* Indirect Branch Prediction Barrier */
