On Sun, Oct 14, 2018 at 10:02 PM Borislav Petkov <[email protected]> wrote: > > On Sun, Oct 14, 2018 at 09:15:00PM +0200, Uros Bizjak wrote: > > The ChangeLog says "real INSTRUCTION mnemonics", e.g. POPCNTQ and POPCNTL. > > Right, INSTRUCTION. > > > The compiler will generate the register name with the correct implied > > width (e.g. %rax for long, %eax for int), so the assembler will be > > able to cross check if operands fit the instruction > > The __arch_hweightXX functions already enforce the proper type and > the inline asm() operands already place the arguments in the proper > registers where the instruction encoding expects them. > > So if you're going to relax this, then you could relax the inline asm > operand specifications too. I say you "could" because then you need to > fix arch/x86/lib/hweight.S too, which would be at least ugly. So I think > we're stuck with %xDI/xAX and %xAX as operands, where 'x' is either 'r' > or 'e'. > > > And there will be a couple of ugly #defines less. > > That's the only advantage of this change AFAICT. How about you reflect > that in your commit message?
No problem, will send v2 with amended message. Uros.
