On Mon, Oct 15, 2018 at 10:59:47AM +0530, Manish Narani wrote:
> Add ddrc memory controller node in dts. The size mentioned in dts is
> 0x30000, because we need to access DDR_QOS INTR registers located at
> 0xFD090208 from this driver.
>
> Signed-off-by: Manish Narani <manish.nar...@xilinx.com>
> ---
> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> index 29ce234..a81d3b16 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> @@ -355,6 +355,13 @@
> xlnx,bus-width = <64>;
> };
>
> + mc: memory-controller@fd070000 {
> + compatible = "xlnx,zynqmp-ddrc-2.40a";
> + reg = <0x0 0xfd070000 0x0 0x30000>;
> + interrupt-parent = <&gic>;
> + interrupts = <0 112 4>;
> + };
> +
> gem0: ethernet@ff0b0000 {
> compatible = "cdns,zynqmp-gem", "cdns,gem";
> status = "disabled";
> --
Still needs DT folks ACK.
--
Regards/Gruss,
Boris.
Good mailing practices for 400: avoid top-posting and trim the reply.
